If you've read my previous post about control hazards, you may have noticed that I talked about branches and jumps, but did not write a single word about function call or return instructions. This omission may be a bit surprising if you are not familiar with RISC-V or architectures with …
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Control hazards with jumps and branches
I've talked about the data hazards in a previous installment, now let's talk about control hazards. A control hazard is when we need to find the destination of a jump or a branch and can't fetch any new instruction until this destination is known.
When a branch instruction is fetched …
read moreI want a hardware multiplier
I'm currently working on the data multiplexer, the part that comes between the CPU and the memory and is responsible for putting the right byte at the right place, but I can't stop thinking about what comes next.
And let me tell you, there's still quite a lot of development …
read moreOf data hazards, bypasses and stalls
Remember that a data hazard occurs when an instruction waits for the result of a previous instruction.
In the following example:
add a0, t0, t1 ; a0 ← t0 + t1 sub a1, a0, t2 ; a1 ← a0 + t2
the
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instruction stores the result into registera0
when it reaches the Writeback stage …Astorisc: The simulation begins
Just a few components ordered
I had some components to buy at Mouser for an unrelated project, but my order wasn't going to reach 50€ and I wouldn't get free shipping...
So I added a few of nearly every logic gate from the AUC family in the basket. These are like the usual 74 LS …
read moreAstorisc: Building blocks and components
Throughout the entire processor, there are a few basic building blocks that will be used in various places. Let's have a look at some of them.
Registers
By far, the block that we'll use the most is the register. Not only in the register file, but also between each stage …
read moreAstorisc: The pipeline stages and hazards
I would like to go more into detail about each stage of the pipeline, what they do and how they work. I know I said in the previous installment that I would not go into the details of hazards, but it looks like I will need it to document my …
read moreAstorisc architecture overview: pipeline
This article is mostly a high-level overview of the Astorisc architecture, do not expect implementation tricks and gory details in here.
As I said in the presentation, I'd like to make Astorisc a pipelined processor. But what does this actually mean? I could send you to the article on Wikipedia …
read moreA RISC-V processor from logic circuits
Now that BB-88 is more or less complete, let me tell you about another project that has been on my mind for a few years now: a homebrew computer featuring a RISC-V processor made of 74 series logic.
There are already a few projects to make a RISC-V processor from …
read moreBB-88 is the new Bidule88
This is a log entry about BB-88. See the project page to know more about it.
Soon after my last post about Bidule88 in 2014, I realized that four breadboards would definitely not be enough to complete the project. I quickly tore it down to restart from scratch, this time …
read moreBidule88 Part 02: It runs!
First achievement with Bidule88: it is actually running some code that I've written and uploaded into its EEPROM! Here is the result:
The parts are connected as described on Homebrew8088 except that the EEPROM I used is bigger. Not that it is needed, though, the code is only a few …
read moreBidule88 Part 01: Introduction