Other articles

  1. Of data hazards, bypasses and stalls

    Remember that a data hazard occurs when an instruction waits for the result of a previous instruction.

    In the following example:

            add a0, t0, t1         ; a0  ←  t0 + t1
            sub a1, a0, t2         ; a1  ←  a0 + t2

    the add instruction stores the result into register a0 when it reaches the Writeback stage …

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  2. Astorisc: The simulation begins

    These last few weeks, I've been working on implementing the CPU in Digital.

    My initial intention was to stay as close as possible to what will be the actual implementation, but in practice, it may not have been a good idea, because it didn't always play well with the simulation …

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  3. Just a few components ordered

    I had some components to buy at Mouser for an unrelated project, but my order wasn't going to reach 50€ and I wouldn't get free shipping...

    So I added a few of nearly every logic gate from the AUC family in the basket. These are like the usual 74 LS …

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  4. Astorisc: Building blocks and components

    Throughout the entire processor, there are a few basic building blocks that will be used in various places. Let's have a look at some of them.


    By far, the block that we'll use the most is the register. Not only in the register file, but also between each stage …

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