I want a hardware multiplier

I'm currently working on the data multiplexer, the part that comes between the CPU and the memory and is responsible for putting the right byte at the right place, but I can't stop thinking about what comes next.

And let me tell you, there's still quite a lot of development to do and many topics to cover!

The next article will probably be about branches and jumps, leaving out everything related to exceptions and interrupts handling for the moment.

On the development side, and in no particular order, there's waiting for slower memory or IO device, actual memory mapping, CSR's and all the system instructions, exceptions and interrupts, global reset circuitry, ...
And then the peripherals.

There is also one thing that may come much later in the project but that I don't want to rule out: a hardware multiplier. (And while at it, why not put a division unit along with it? But that is another story.)

In any case, there's just no way that it will run in a single cycle, so it will require some sort of mechanism to freeze the pipeline at the Execute stage while the "MulDiv" unit does its job. I expect this mechanism to be very similar to what I'll have to implement for the slow memory access anyway.

Regarding the multiplier itself, chances are that I will go for simplicity and do the slowish shift-add method because all the other ways I know are just too expensive to build with discrete gates at 32 bits.

And before you ask, no, I will not go out of order. The instruction following a mul will have to wait in the Decode stage!

Now, honestly, wouldn't it be very sad to have to draw the Mandelbrot set using only software multiplication?

Other articles

Of data hazards, bypasses and stalls
mar 28 juin 2022
By Amand Tihon

In Electronics.

tags: RiscV

Remember that a data hazard occurs when an instruction waits for the result of a previous instruction.

In the following example:
```
        add a0, t0, t1         ; a0  ←  t0 + t1
        sub a1, a0, t2         ; a1  ←  a0 + t2
```
the add instruction stores the result into register a0 when it reaches the Writeback stage …
read more
Astorisc: The simulation begins

lun 09 mai 2022
By Amand Tihon

In Electronics.

tags: RiscV

These last few weeks, I've been working on implementing the CPU in Digital.

My initial intention was to stay as close as possible to what will be the actual implementation, but in practice, it may not have been a good idea, because it didn't always play well with the simulation …
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Just a few components ordered

jeu 14 avril 2022
By Amand Tihon

In Electronics.

tags: RiscV

I had some components to buy at Mouser for an unrelated project, but my order wasn't going to reach 50€ and I wouldn't get free shipping...

So I added a few of nearly every logic gate from the AUC family in the basket. These are like the usual 74 LS …
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Astorisc: Building blocks and components

mar 29 mars 2022
By Amand Tihon

In Electronics.

tags: RiscV

Throughout the entire processor, there are a few basic building blocks that will be used in various places. Let's have a look at some of them.

Registers

By far, the block that we'll use the most is the register. Not only in the register file, but also between each stage …
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Astorisc: The pipeline stages and hazards

mar 18 janvier 2022
By Amand Tihon

In Electronics.

tags: RiscV

I would like to go more into detail about each stage of the pipeline, what they do and how they work. I know I said in the previous installment that I would not go into the details of hazards, but it looks like I will need it to document my …
read more
Astorisc architecture overview: pipeline

dim 10 octobre 2021
By Amand Tihon

In Electronics.

tags: RiscV

This article is mostly a high-level overview of the Astorisc architecture, do not expect implementation tricks and gory details in here.

As I said in the presentation, I'd like to make Astorisc a pipelined processor. But what does this actually mean? I could send you to the article on Wikipedia …
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A RISC-V processor from logic circuits

mer 22 septembre 2021
By Amand Tihon

In Electronics.

tags: RiscV

Now that BB-88 is more or less complete, let me tell you about another project that has been on my mind for a few years now: a homebrew computer featuring a RISC-V processor made of 74 series logic.

There are already a few projects to make a RISC-V processor from …
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Other articles

Registers