A RISC-V processor from logic circuits

RISC-V logo Now that BB-88 is more or less complete, let me tell you about another project that has been on my mind for a few years now: a homebrew computer featuring a RISC-V processor made of 74 series logic.

There are already a few projects to make a RISC-V processor from scratch in various stages of completion:

  • The first one I've heard of was Robert Baruch's LMARV-1 (Learn Me A Risc V), a series of youtube videos. The first iteration of the project apparently hit a hard stop at some point, but got rebooted in late 2020. These videos cover many interesting topics like various ways to implement the register file, the ALU, etc.
  • The second one was a project on Hackaday.io by Phil Wright: World's first 32bit Homebrew CPU
  • The latest one is the Pineapple ONE, by Filip Szkandera. This is probably the most advanced of these projects, and perhaps the only one that can actually be used to run some real code.

Also, not a RISC-V, but close enough, there is the Spaceage 2, a university project that implements the MIPS ISA.

All of these projects aimed for different goals, and each one follows its own path, which make them all very interesting to study.

I don't know if mine will ever see the light of day, not even speaking of being complete, but I'll try1 to keep some notes about my research and progress here.


My main goal for this project is simple to state: make it as fast as I can!

At the moment, I envision a pipelined CPU running maybe at 30MHz with register forwarding between some stages of the pipeline to avoid stalls. The main path in the pipelined would not be microcoded, unlike most projects I've seen. That said, if I ever implement hardware multiplication and division, they will take multiple cycles to execute and would probably be microcoded.

My second goal is to make it a Von Neuman architecture, where there is a single memory space for both code (instructions) and data. This goes against the first goal because instructions that need to access the memory will prevent the CPU from fetching the next instruction during the same clock cycle, but I reckon this is the price to pay for the flexibility of a "real" computer.

Finally, I'm not only thinking about the processor here, but also the peripherals and the way they communicate together to make an actual computer. That means there will be some kind of bus, probably like the ISA bus but wider, wait-states to cope with slower devices, etc.

How do we call it ?

Unless I find a better name in the future, I'm still undecided between Astorisc and Castorisc. The first one is for Alrj's take on RISC-V and is similar to the word Asterisk. The second one doesn't stand for anything, it only evolved from the first idea and could use a castor as a logo.

Sometimes, finding project names is even harder than finding hostnames.

Where does it happen ?

Right here! There will be a project page where I will hopelessly try to organize my thoughts.

Stay tuned!

  1. If you used to follow my defunct blog or even this very website in the past, you will assume there is a fairly high probablility that I will stop publishing anything about the project very soon. and you may very well be right about it. We'll see...