Alrj's take on RISC-V.
Astorisc is my project of a RISC-V computer made from scratch. It is in the very early stages of research, development hasn't really started yet.
- Project introduction
- Pipeline overview
- Pipeline hazards
- Building blocks
- Just a few components ordered
- Astorisc: The simulation begins
- Of data hazards, bypasses and stalls
- I want a hardware multiplier
- Control hazards with jumps and branches
- A word on function calls and returns
- Use only components that are still in production; this is not a retro-computing project.
- Register file: Asynchronous Static RAM? Synchronous Static RAM? Single-port or multi-port? Actual flip-flops?
- System memory: probably fast Asynchronous Static RAM that can be accessed in one cycle
- Prefetch queue or not? Or a prefetch line, like a one-line cache?
- How do I handle interrupts?
There are also a few things I'm pretty confident I will not implement, such as an MMU, or the multiple privileges levels inside the CPU.
This page will start more as a collection of links to external resources, in random order.
- First of all, there is the RISC-V Unprivileged Spec but also the Privileged Spec that contains the sections about the Control and Status Registers (CSRs) and interrupt modes.
- The forum at 6502.org features some very interesting threads:
- A comparator for two's complement explains how to adapt a magnitude comparator so that it can compare signed numbers as well.
- Padraig Edgington does a fantastic job explaining how to implement iterative multiplication and division in hardware:
- Several teachers and universities have also uploaded their lectures about processor architecture to Youtube. Some of them are based on MIPS (which is very similar), but there's also a fair amount that are more specifically about RISC-V.